PIC Micro controller
The Microcontroller has many more reasons to be used than the microprocessors. The difference between the Microprocessors and Microcontrollers are given below.
Difference between Microprocessors and Microcontrollers
MICROPROCEESOR MICROCONTROLLER
1. No memory Got Separate ROM and RAM
2. No I/O Ports In built Ports Available
3. No Timers Internal Timers Available
4. No Serial Port In built Serial Communication
5. Von Neumann Architecture Harvard Architecture
Other than the normal Microcontrollers PIC Family supports more features, so we have chosen PIC 16F877 as the main controller. The Main Features and Peripherals are discussed below.
Core Features:
• High performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program Branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
• Interrupt capability (up to 14 sources)
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• Low-power consumption:
- < 0.6 mA typical @ 3V, 4 MHz
- < 1 µA typical standby current
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI (Master mode) and 12C(Master/Slave)
• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection
• Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only)
DEVICE OVERVIEW
This document contains device specific information. Additional information may be found in the PICmicro™ Mid-Range Reference Manual (DS33023). There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data
sheet. The PIC16F877/874 devices come in 40-pin packages. The Parallel Slave Port is not implemented on the 28-pin devices. The PIC16F877 Block diagram is
PIC16f877 Pin Diagram:
PINOUT DESCRIPTION:
MEMORY ORGANIZATION
There are three memory blocks in each of the PIC16F87X MCUs. The Program Memory and Data Memory have separate buses so that concurrent
access can occur and is detailed in this section.
Program Memory Organization:
The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory. Accessing a location above the physically implemented address will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h.
Data Memory Organization:
The data memory is partitioned into multiple bankswhich contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>)and RP0 (STATUS<5>) are the bank select bits.Each bank extends up to
7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access.
SPECIAL FUNCTION REGISTERS:
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section.
STATUS Register:
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Further more, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended.For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. Forother instructions not affecting any status bits, see the“Instruction Set Summary."
STATUS REGISTER :(ADDRESS 03h, 83h, 103h, 183h)
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
INTCON Register:
The INTCON Register is a readable and writable register,which contains various enable and flag bits for theTMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
INTCON REGISTER :(ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software).
PIE1 Register :
The PIE1 register contains the individual enable bits for the peripheral interrupts.
PIE1 REGISTER :(ADDRESS 8Ch)
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
PIR1 REGISTER (ADDRESS 0Ch):
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
PCL and PCLATH:
The program counter (PC) is 13-bits wide. The low bytecomes from the PCL register, which is a readable andwritable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situationsfor the loading of the PC. The upper example in the figureshows how the PC is loaded on a write to PCL(PCLATH<4:0> PCH). The lower example in the figureshows how the PC is loaded during a CALL or GOTOinstruction (PCLATH<4:3> PCH).
Indirect Addressing, INDF and FSR Registers:
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.Indirect addressing is possible by using the INDF register.Any instruction using the INDF register actually accesses the register pointed to by the File Select Register,FSR. Reading the INDF register itself, indirectly(FSR = ’0’) will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-6.
I/O PORTS:
Some pins for these I/O ports are multiplexed with an alternate function for the Peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
PORTA and the TRISA Register:
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, where as writing to it will write to the port latch. All write operations are read-modify-write operations.Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Three pins of PORTB are multiplexed with the Low Voltage Programming function: RB3/PGM, RB6/PGC and RB7/PGD. PORTB pins has a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF.A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This interrupt-on-mismatch feature, together with software onfigureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, “Implementing Wake-up on Key Strokes” (AN552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>).
PORTC and the TRISC Register:
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions.
When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output,while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify write instructions (BSF, BCF, XORWF) with TRISC as destination, should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTD and TRISD Registers:
PORTD is an 8-bit port with Schmitt Trigger input buffers.Each pin is individually configureable as an input or output.PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PORTE and TRISE Register:
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6,and RE2/CS/AN7) which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers.The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make certain that the TRISE<2:0> bits are set, and that the pins are configured as digital inputs. Also ensure that ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL.
ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER
TRANSMITTER (USART):
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs etc. The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.The USART module also has a multi-processor communication capability using 9-bit address detection.
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
bit 7 CSRC: Clock Source Select bit
Asynchronous mode: Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode: Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data, can be parity bit
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode: Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave: Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware)
USART Baud Rate Generator(BRG):
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate.Table shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table. From this, the error in baud rate can be determined. It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases.Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
USART Asynchronous Mode:
In this mode, the USART uses standard non-return-to zero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
USART ASYNCHRONOUS TRANSMITTER:
The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register.
Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty.Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock. The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, when transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter.
As a result, the RC6/TX/CK pin will revert to hi-impedance.In order to select 9-bit transmission, transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register.
When setting up an Asynchronous Transmission, follow these steps:
1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH.
2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit bit TX9.
5. Enable the transmission by setting bit TXEN, which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.
7. Load data to the TXREG register (starts transmission).
8. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON
register are set.
USART ASYNCHRONOUS RECEIVER:
The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit, which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty.
If the RCREG register is still full, the overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software.This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, and no further data will be received. It is therefore,essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA<2>) is set if a STOP bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information.
ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE:
The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the other devices. The A/D conversion of the analog input signal results in a corresponding 10-bit digital number. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D clock must be derived from the A/D’s internal RC oscillator.The A/D module has four registers. These registers are:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 11-2, configures the functions
of the port pins. The port pins can be configured as analog inputs (RA3 can also be the voltage reference), or as digital I/O.Additional information on using the A/D module can be found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).
REGISTER 11-1: ADCON0 REGISTER (ADDRESS: 1Fh)
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2 GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1 Unimplemented: Read as '0'
bit 0 ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
These steps should be followed for doing an A/D Conversion:
1. Configure the A/D module:
• Configure analog pins/voltage reference and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared (with interrupts enabled); OR
• Waiting for the A/D interrupt
6. Read A/D result register pair (ADRESH:ADRESL), clear bit ADIF if required.
7. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before the next acquisition starts.
RESET:
The PIC16F87X differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a “RESET state” on Power-on Reset (POR), during SLEEP,
INTERRUPTS:
The PIC16F87X family has up to 14 sources of interrupt.The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits.A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set,regardless of the status of the GIE bit.
The GIE bit is cleared on RESET.The “return from interrupt” instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts.The RB0/INT pin interrupt, the RB port change interrupt,and the TMR0 overflow interrupt flags are contained in the INTCON register.The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2. The corresponding
interrupt enable bits are contained in special function registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON.
When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or GIE bit.
Note: Individual interrupt flag bits are set, regardless of the status of their corresponding
mask bit, or the GIE bit.
INSTRUCTION SET SUMMARY:
Each PIC16F87X instruction is a 14-bit word, divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F87X instruction set summary in byte-oriented, bit-oriented,and literal and control operations. The below Table shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file register designator and ’d’ represents a destination designator.The file register designator specifies which file register is to be used by the instruction.The destination designator specifies where the result of the operation is to be placed. If ’d’ is zero, the result is placed in the W register. If ’d’ is one, the result is placed in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field designator which selects the number of the bit affected by the operation, while ’f’ represents the address of the file in which the bit is located.
For literal and control operations, ’k’ represents an eight or eleven bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
Interface With PC
Even if all the parameters are processed through a PIC Microcontroller the display unit used will be an Sevensegment Display or an LCD Display. Using this Devices we cannot make Parameter more effective. In order to make the Parameter more effectively illustrated on Screen we can go for PC instead of LCD Displays. So to Interface a PC with our Microcontroller unit We need a RS232 interface. Here we have used MAX232 as a serial interface chip.
MAX 232
The Max 232 is a dual RS-232 receiver / transmitter that meets all EIA RS232C specifications while using only a +5V power supply. It has 2 onboard charge pump voltage converters which generate +10V and –10V power supplies from a single 5V power supply. It has four level translators, two of which are RS232 transmitters that convert TTL\ CMOS input levels into + 9V RS232 outputs. The other two level translators are RS232 receivers that convert RS232 inputs to 5V 
TTL\CMOS output level. These receivers have a nominal threshold of 1.3V, a typical hysterisis of 0.5V and can operate upto + 30V input. 1. Suitable for all RS232 communications.
2. +12V power supplies required.3. Voltage quadrapular for input voltage upto 5.5V (used in power supply Section of computers, peripherals, and modems).
Three main sections of MAX232 are
1. A dual transmitter
2. A dual receiver
3. +5V to + 10V dual charge pump voltage converter.Power supply section
The MAX232 power supply section has 2 charge pumps the first uses external capacitors C1 to double the +5V input to +10V with input impedance of approximately 200W. The second charge pump uses external capacitor to invert +10V to –10V with an overall output impedance of 45W.
The best circuit uses 22mF capacitors for C1 and C4 but the value is not critical. Normally these capacitors are low cost aluminium electrolyte capacitors or tantalum if size is critical. Increasing the value of C1 and C2 to 47mF will lower the output impedance of +5V to+10V doubler by about 5W and +10V to -10V inverter by about 10W. Increasing the value of C3 and C4 lowers the ripple on the power supplies thereby lowering the 16KHz ripple on the RS232 output. The value of C1 and C4 can be lowered to 1mF in systems where size is critical at the expense of an additional 20W impedance +10V output and 40W additional impedance at –10V input.
Tansmitter section:
Each of the two transmitters is a CMOS inverter powered by + 10V internally generated supply. The input is TTL and CMOS compatible with a logic threshold of about 26% of Vcc. The input if an unused transmitter section can be left unconnected: an internal 400KW pull up resistor connected between the transistor input and Vcc will pull the input high forming the unused transistor output low.
The open circuit output voltage swing is guaranteed to meet the RS232 specification + 5v output swing under the worst of both transmitter driving the 3KW 
Minimum load impedance, the Vcc input at 4.5V and maximum allowable ambient temperature typical voltage with 5KW and Vcc= +.9 vThe slow rate at output is limited to less than 30V/ms and the powered done output impedance will be a minimum of 300W with +2V applied to the output with Vcc =0V.The outputs are short circuit protected and can be short circuited to ground indefinitely. Reciever section
The two receivers fully conform to RS232 specifications. They’re input impedance is between 3KW either with or without 5V power applied and their switching threshold is within the +3V of RS232 specification. To ensure compatibility with either RS232 IIP or TTl\CMOS input. The MAX232 receivers have VIL of 0.8V and VIH of 2.4V the receivers have 0.5V of hysterisis to improve noise rejection.
The TTL\CMOS compatible output of receiver will be low whenever the RS232 input is greater than 2.4V. The receiver output will be high when input is floating or driven between +0.8V and –30V.
Electrical characteristics of MAX232
Vcc = 6v V+ = 12v V- = 12v
Input voltage :
T1in,T2in : -0.3 to (Vcc+ 0.3v)
R1in,R2in : +30v or –30v
Output voltage:
T1out, T2out : ((V+)+0.3v) to ((V-)+0.3v)
R1out, R2out : -0.3V to (Vcc+0.3V)
Power dissipation : 375mW
Output ressistance :300W
